As you might know, since verilog 2001, wires are implicitly declared in verilog.That means you can start using a net in verilog and assume as if you declared it as a single bit wire. The important thing to notice here is that as long as you use it as a single bit wire, you are safe.
If verilog was "C" , i would have appreciated this feature or called it as an "enhancement".

But it is not. Verilog is meant to write RTLs. While writing RTL, the more you are forced to be specific ,the lesser error prone you are making the environment.